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[VHDL-FPGA-Verilog] di

Description: 应用VHDL语言编写设计一个正负脉宽可控的4分频的分频器。程序简单易懂；-Application of VHDL language to design a controlled positive and negative pulse frequency divider 4. Procedures are simple and easy to understand
Platform: | Size: 10240 | Author: 小杰 | Hits:

[VHDL-FPGA-Verilog] 61EDA_D807

Description: VHDL数频分频器设计 整数，奇数，偶数，半数等的分频 -VHDL design of an integer number of frequency divider, odd, even, half of the frequency, etc.
Platform: | Size: 322560 | Author: 黄家福 | Hits:

[VHDL-FPGA-Verilog] fenpin

Description: 7分频器 是指将不同频段的声音信号区分开来，分别给于放大，然后送到相应频段的扬声器中再进行重放。在高质量声音重放时，需要进行电子分频处理-seven frequency divider
Platform: | Size: 52224 | Author: 华安 | Hits:

[VHDL-FPGA-Verilog] fenpin-FPGA

Description: 本文通过在QuartursⅡ开发平台下，一种能够实现等占空比、非等占空比整数分频及半整数分频的通用分频器的FPGA设计与实现，介绍了利用VHDL硬件描述语言输入方式，设计数字电路的过程。-In this paper, the development platform in Quarturs Ⅱ, one can achieve such duty, such as the duty cycle of non-integer frequency division and semi-integer frequency divider of the FPGA general-purpose design and implementation, describes the use of VHDL hardware description language input , digital circuit design process.
Platform: | Size: 17408 | Author: liu | Hits:

[VHDL-FPGA-Verilog] zq_100us

Description: 利用VHDL实现偶数分频，设计了一种能够实现等占空比的任意偶数分频、等占空比任意奇数分频、不等占空比的任意半整数分频的较为通用的分频器,并通过QuartusII进行了功能仿真。 -Use VHDL to achieve an even frequency, designed to achieve such a duty cycle of any even frequency, such as the duty cycle divide any odd number, ranging from any duty semi-integer frequency divider of the more common and carried out by QuartusII functional simulation.
Platform: | Size: 1024 | Author: liu | Hits:

[VHDL-FPGA-Verilog] 002

Description: VHDL语言 用计数器实现分频 N频分频器-VHDL language divide by N counter frequency divider to achieve
Platform: | Size: 3072 | Author: xiaojing | Hits:

[Embeded-SCM Develop] SingleLoopSDM_prj

Description: 对频率综合器中的小数分频器进行优化配置，减小参考杂散。-Of the fractional frequency divider in the synthesizer to optimize the configuration, reducing the reference spur.
Platform: | Size: 854016 | Author: weijianjun | Hits:

[VHDL-FPGA-Verilog] frequency5x2

Description: frequency5x2实现频率的分频，5*2即实现10分频，主要用于满足有些控制类的频率时钟。-frequency5x2 realize the frequency divider, 5* 2 frequency of achieving 10 points, mainly used to control the class to meet some of the frequency of the clock.
Platform: | Size: 3072 | Author: 吴海勇 | Hits:

[VHDL-FPGA-Verilog] 5fenpin

Description: vhdl的时钟信号分频 5分频电路代码 将任意频率5分频-vhdl clock signal frequency divider circuit 5 code any frequency band 5
Platform: | Size: 15360 | Author: 王涛 | Hits:

[VHDL-FPGA-Verilog] freqdivider

Description: Frequency divider application for Verilog programming
Platform: | Size: 1024 | Author: Mark Ko | Hits:

[VHDL-FPGA-Verilog] DIV_5

Description: 该源码包包含一个奇分频分频器的Verilog代码及其测试代码。奇分频在许多分频电路中都会用到。-The source code package contains a surprising frequency divider in Verilog code and test code. Odd number of points in the frequency divider circuit will be used in.
Platform: | Size: 1024 | Author: 杨宗凯 | Hits:

[Embeded-SCM Develop] yanshichengxu

Description: 只用单片机实现20Mhz不现实,但可以把频率信号分频,比附超过100K之后就给他2分频,随着频率增加,分频值增加,分频电路需另加硬件,然后分档,分档后的频率测量程序可以用下面的方法测量.- 20Mhz MCU only unrealistic, but the frequency of the signal frequency, after the analogy gave him more than 100K divided by 2, as the frequency increases, the value of increased frequency, frequency divider circuit are subject to hardware, and then sub-file, sub-file after the frequency measurement process can be measured using the following method.
Platform: | Size: 4096 | Author: suzhou | Hits:

[VHDL-FPGA-Verilog] verilog1

Description: 用verilog语言编写的6分频分频计数器。分频后用来控制蜂鸣器响，也可以修改代码做成更高分频的计数器。压缩包内也包含此分频器的modelsim仿真文件-Verilog language with 6 frequency divider counter. Frequency and used to control the buzzer sound, you can modify the code to make a higher frequency counter. Compressed package also contains this file divider modelsim simulation
Platform: | Size: 143360 | Author: 广子 | Hits:

[VHDL-FPGA-Verilog] PLL_12MHz

Description: 用verilog语言制作一个PLL，这个PLL可以将频率除频到12MHZ，将PLL除频成12MHZ输出-Verilog language production with a PLL, the PLL frequency divider can be to 12MHZ, 12MHZ into the PLL output divider
Platform: | Size: 55296 | Author: 郑先生 | Hits:

[SCM] cunchuqishuaxin

Description: 将信号波形数据存放在EEROM中，通过74LS393分频产生不同频率的刷新信号，输出存储器的数据，由DA输出，产生不同频率的信号。. -The signal waveform data stored in EEROM, through the 74LS393 frequency divider to produce different frequency refresh signal, output of memory data, output by the DA, generate signals of different frequency.
Platform: | Size: 84992 | Author: 刘清 | Hits:

[VHDL-FPGA-Verilog] Frequency-counter

Description: 基于FPGA的数字频率计：1. 测量1Hz～1GHz方波的频率，精度为十分位。 2. 档位自动调整，分为1Hz~999.9Hz,1KHz~999.9KHz,1MHz~999.9MHz三个档位。 3. 实现16位的除法器，进行频率的计算，并以ASIIC码输出测量的数据。 -FPGA-based digital frequency meter: 1. Measurement 1Hz ~ 1GHz square wave frequency, accuracy decile. (2) automatically adjusts the stalls, divided into 1Hz ~ 999.9Hz, 1KHz ~ 999.9KHz, 1MHz ~ 999.9MHz three stalls. 3 for 16-bit divider, the frequency calculations, and ASIIC code output measured data.
Platform: | Size: 133120 | Author: 曾 | Hits:

[VHDL-FPGA-Verilog] fenpin_m

Description: 基于VHDL的一种小数分频器，能够实现任意的小数分频-A decimal frequency divider base on VHDL, be able to achieve any decimal frequency divider
Platform: | Size: 1024 | Author: liu | Hits:

[SCM] pinglvji

Description: 硬件电路主要分为信号转换电路、分频电路、数据选择电路、单片机系统和显示电路五部分。 电平转换电路： 电平转换电路的必要性：因为在单片机计数中只能对脉冲波进行计数，而实际中需要测量的频率的信号是多种多样的，有脉冲波，还有可能有正弦波、三角波等，所以需要一个电路把待测信号可以进行计数的脉冲波。 通过电平转化电路将正弦输入信号fx整形成同频率方波fo,要将正弦信号转换成方波信号可以用过零比较电路实现。正弦信号通过LM833N与零电平比较，电压大于零的时候输出LM833N的正电源+5V，电压小于零的时候输出负电源0V。 -Hardware circuit can be divided into signal conversion circuit, frequency divider circuit, the data selection circuit, single-chip systems, and display circuit of five parts. Level-shifting circuit: The need for level-shifting circuit: as in the MCU can only count on the pulse count, but the actual need to measure the frequency of the signal is varied, a pulse wave, there may be sine, triangle, etc. so they need a circuit to test the signal pulse can be counted. By the level conversion circuit to form a sinusoidal input signal with frequency fx entire square wave fo, convert square wave to sine wave signal can be used to achieve zero comparator circuit. Sinusoidal signal with the zero level by LM833N comparison, the voltage output of LM833N greater than zero when the positive power supply 5V, output voltage is less than zero, the negative power supply 0V.
Platform: | Size: 412672 | Author: 华一 | Hits:

[VHDL-FPGA-Verilog] VHDLBasicExperimentSJTU

Description: 上海交大几个基础VHDL 实验的代码,包括分频器，计数器，七段计数器，状态机，锁存器等-Shanghai Jiaotong University and a few experiments of basic VHDL code, including the frequency divider, timer, seven segment counter, state machines, latches, etc.
Platform: | Size: 865280 | Author: 魏玉萍 | Hits:

[VHDL-FPGA-Verilog] sync_signals

Description: Double-FF synchronization stage and frequency divider.
Platform: | Size: 1024 | Author: macondo | Hits:
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